module flow_led(
 input  wire  clk,
 input  wire  rst_n,
 output reg   [3:0]led);
 
   reg [3:0] cstate;
   reg  [3:0] nstate;
   reg   [24:0] cnt;
   parameter cnt_max=25'd24999999;
   
    localparam  led_0=4'b0001,
	                    led_1=4'b0010,
			led_2=4'b0100,
			led_3=4'b1000;
	
	
    always@(posedge clk  or negedge  rst_n)begin
	 if(!rst_n)
	 cnt<=25'b0;
	 else if (cnt==cnt_max)begin
	 cnt <=25'b0 ;
	 end
	 else cnt <=cnt+1'b1 ; 
	      end 
	always@(posedge clk or negedge  rst_n)begin
	if(!rst_n)
	cstate<=led_0;
	else cstate<=nstate;
        	end
	always@(*)begin
          nstate=led_0;
		  case(cstate)
		  led_0:begin if(rst_n) nstate<=led_1;
		                         else  nstate<=led_0;end
							led_1: begin if(rst_n) nstate<=led_2;
		                         else  nstate<=led_0;end
								 led_2:begin if(rst_n) nstate<=led_3;
		                         else  nstate<=led_0;end
								 led_3:begin if(rst_n) nstate<=led_0;
		                         else  nstate<=led_0;end
                  end
				  always@(cstate) begin
				  led_0:led<=4'b1000;
				  led_1:led<=4'b0100;
				  led_2:led<=4'b0010 ;
				  led_3:led<=4'b0001;
				  default:led<=4'b1000;
	end
	endmodule
			
			
      